Digital speed gate for doppler radar

ABSTRACT

A speed gate for a pulse Doppler or CW Doppler radar wherein a signal being tracked is fed, along with a signal from a digitally controlled oscillator, to an exclusive OR gate ro derive gating signals for clock pulses. such gated clock signals are then used to actuate an up-down counter to derive a digital number indicative of the average phase difference between the signal being tracked and the digitally controlled oscillator. Such number is combined with a digital number indicative of the phase difference, measured by the gated clock signals over a relatively short period, between the signal being tracked and the signal out of the digitally controlled oscillator to produce a digital correction signal for the digitally controlled oscillator to change the phase thereof until a phase lock condition occurs between the signals into the exclusive OR gate.

nited States Patent Mead Feb. 6, 1973 [54] DIGITAL SPEED GATE FORDOPPLER Primary Examiner-T. H. Tubbesing RADAR AttrneyPhili .l.McFarland and Jose h D. Pannone [75] Inventor: George S. Mead, Maynard,Mass. [57] ABSTRACT [73] Asslgnee: fi Company Lexington A speed gate fora pulse Doppler or CW Doppler S radar wherein a signal being tracked isfed, along with [22] Filed: Sept. 30, 1970 a signal from a digitallycontrolled oscillator, to an exelusive OR gate ro derive gating signalsfor clock pul- [211 Appl' 76954 ses. such gated clock signals are thenused to actuate an up-down counter to derive a digital number indica-[52] U S C| 343 A, 331 1 A 343 5 p tive of the average phase differencebetween the signal 543 being tracked and the digitally controlledoscillator. 51 Int. Cl ..G01s 9 44 such number is with a digital number[58] Field of Search 343/5 DP 7 A 331/] A dicative of the phasedifference, measured by the gated clock signals over a relatively shortperiod, between the si nal bein tracked and the si nal out of 56 R r g gg I 1 e erences cued the digitally controlled oscillator to produce adigital UNITED STATES PATENTS correction signal for the digitallycontrolled oscillator to change the phase thereof until a phase lockcondilsfhaefer tion occurs between the signals into the exclusive ORross......... 3,449,691 6/1969 Pasternack et al ..331/1 A x gate 4Claims, 1 Drawing Figure s a LIMITING EXCLUSIVE AVIERAGE com: RENTAMPL'F'ER 0R GATE COUNTER PULSE 35 TRANSMITTER ARECEIVER RANGE GATE 5/39 1M g ERROR 21x ADDER 43 I VARIABLE I I3 asst IL wa TEM DlG lTA LLcoWREL o 0EILTAfiR Q, "l S E TRIGGER 24 l GENERATOR g utcuue COUNTERREGISTER ADDER I 45 i O L.L ;;T; J 1 53 55 co 0p 57 C P LI S 755G116 ArW ur iIzarloi? l GENERATOR cp dw u gg DETECTOR}7, m'EWcE }-"S 250 59 iMi. i EXCLUSIVE Low PASS LOCK 0R GATE j FILTER INDICATOR DIGITAL SPEEDGATE FOR DOPPLER RADAR The invention herein described was made in thecourse of or under a contract or subcontract thereunder, with theDepartment of Defense.

BACKGROUND OF THE INVENTION It is known in the radar art that a Dopplertracker, commonly referred to as a speed gate", may be used to advantagein lieu of a bank of Doppler filters in either a pulse Doppler orcontinuous wave Doppler radar. The principle of operation of the usualspeed gate is similar to the principle of operation of the wellknown AFCcircuit ordinarily used in FM radio modified so as to phase lock a localoscillator with the received signal. That is, an analog correctionsignal, the magnitude and polarity of which is indicative of the phasedifference between a signal being tracked and a local oscillator signal,is applied to such oscillator in such a manner as to force such phasedifference to a predetermined value and the frequency difference tozero. The local oscillator in the justmentioned type of system is aradio frequency voltage-controlled oscillator, as a klystron, referredto hereinafter as the VCO.

While satisfactory speed gates have been in use for many years, it hasbeen recognized in the field that the use of analog techniques is notideal. For example, it is necessary to adjust the VCO periodically tocompensate for drift thereof or to accept reduced in-service accuracy ofoperation. If such adjustment is not made and the Doppler shift due to atarget approaches the Doppler shift due to clutter, accuracy may bereduced to such an extent as to render the speed gate incapable ofproper operation.

The shortcomings of analog techniques, as is well known, may be overcomeby using digital techniques. Thus, it is theoretically possible toreplace the conventional VCO with a digitally controlled oscillator,hereinafter sometimes referred to as the DCO in a speed gate, usingappropriate converters in the control loop to change from analog todigital signals and viceversa. In practice, however, the requiredconverters are so complex as to make such an approach infeasible.

Therefore, it is a primary object of this invention to provide animproved speed gate for a pulse Doppler or CW Doppler radar system usingdigital techniques.

Another object of this invention is to provide an improved speed gatefor a pulse Doppler or CW Doppler radar system which uses a digitallycontrolled oscillator.

Still another object of this invention is to attain the foregoingobjects using known conventional devices and circuits.

SUMMARY OF THE INVENTION These and other objects of this invention areattained generally by providing a speed gate for either a pulse Doppleror CW Doppler radar system in which: (a) the phase difference betweenthe output of a digitally-controlled oscillator and the echo signal froma target being tracked is continuously measured by counting clock pulseswhich are gated in accordance with such difference; (b) generating adigital correction signal weighted in a predetermined manner inaccordance with the average, over a selected period, and theinstantaneous value of such difference; and, (c) applying suchcorrection signal to the digitally controlled oscilla- BRIEF DESCRIPTIONOF THE DRAWING The single FIGURE is a simplified block diagram of acoherent pulse Doppler radar system showing in detail the arrangement ofthe contemplated speed gate.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the FIGURE itmay be seen that a system according to this invention includes aconventional clock pulse generator 11, system trigger generator 13,coherent pulse transmitter/receiver l5, antenna 17, limiting amplifier19, variable delay circuit 21 and range gate 23 arranged as indicated toproduce an interrogating pulse and echo signals from illuminated targets(not shown) at the output of the limiting amplifier 19. The limitingamplifier 19 is a conventional hard" limiter. It will be recognized thatthe signals at the output of the limiting amplifier 19 contain, inaddition to echo signals from any targets by the range gate 23, somenoise signals. The latter appear in the signal out of the limitingamplifier 19 as a square wave of random periodicity in contrast with theecho signals which are periodic square waves. In addition, in order toprovide range gated clock pulses to the circuits to be described so thatecho signals from unwanted targets may not affect operation of thecontemplated speed gate, an AND gate 24 is enabled by the range gate 23.

The train of gated signals out of the limiting amplifier 19 is fed toone input terminal of an exclusive OR gate 25 and to one input terminalof an exclusive OR gate 25a. The second input terminal of the exclusiveOR gate 25 is connected to a terminal (not numbered) of a digitallycontrolled oscillator 29, referred to as DCO 29 and described in moredetail hereinafter. Suffice it to say here that the signal out of DCO 29to exclusive OR gate 25 is a square wave differing in phase by from thesignal at the output terminal (not numbered) of the DCO 29 to exclusiveOR gate 25a.

The exclusive OR gate 25 operates in a known manner to produce a onewhen its two input signals are out of phase and to produce a zero" whenthe two are in phase. It may be seen, therefore, that if, as is the casehere, the output of the exclusive OR gate 25 is connected directly to anAND gate 31 and, through an inverter 33, to an AND gate 35, the formergate is enabled when the input signals to the exclusive OR gate 25 areout of phase and the latter gate is enabled when the two such inputs arein phase. Thus, gated clock pulses from AND gate 24 are passed througheither AND gate 31 or 35. The clock rate may be varied within widelimits so long as the frequency of the clock pulses is greater thantwice the maximum frequency of the output signals from the exclusive ORgate 25, so as to meet the Nyquist sampling criterion under allconditions. The clock pulses, after gating through the AND gates 31, 35are passed to a binary up-down counter 37 of conventional constructionso as to cause that element, say, to count up one for each clock pulsepassed through AND gate 31 and to count down one for each clock pulsepassed through AND gate 35. A moments thought will make it clear that,assuming a phase lock condition to exist between the signals from theDCO 29 and the signals out of the limiting amplifier 19, the outputsignal from the exclusive OR gate 25 will be a symmetrical square waveat twice the frequency of the two input signals. As a result, under theassumed condition, the AND gates 31, 35 will be enabled for equalperiods and the binary up-down counter 37 will receive an equal numberof up one counts and down one counts. lt is also obvious that, if aphase lock does not exist between the two signals, the output of theexclusive OR gate 25 will be an asymmetric square wave and that,depending on existing conditions, a greater number of either up onecounts or down one counts will be passed to the binary up-down counter37 so that the total count of that element is indicative of theunbalance between up one and down one signals over a period of time. Inother words, the binary up-down counter 37 acts as a digital integratorwhich operates linearly so long as it is not filled. The condition ofthe last stage of the binary updown counter 37 may be used to determinethe sign of the integration process, i.e., whether an excess of up oneor down one counts exists. Similarly, by providing a larger capacitythan would intuitively be required for the binary up-down counter 37,the average of the integration process over a period of time greaterthan the period of the signals out of the exclusive OR gate 25 may bedetermined by disregarding the least significant counts therein. Theoutput of a number of more significant counts, i.e., the averageindicated difference between up one and down one counts out of thebinary up-down counter 37 are fed to an error adder 39, as shown, alongwith the gated clock pulses out of the AND gates 31, 35. The output ofthe error counter 39 then is equal to the average plus the differencebetween the up one and down one" counts during each period of thesignals out of the exclusive OR gate 25. Such a binary signal is thenfed, as shown, to an adder 41 in the DCO 29 along with a binary signalfrom a frequency setter 43. The latter element in a practical case wouldbe a computer (not here shown) adapted to produce a signal to set theDCO 29 roughly to a frequency at which phase lock would occur for anygiven signal being tracked. Such a signal is not essential to thisinvention because it merely reduces the capacity required in the errordetection circuits just described. In the illustrated example, thefrequency setter 43 simply consists of a number of single pole switches(not numbered) which may be selectively actuated so as to impress avoltage from a source (not numbered) on desired ones of the inputs tothe adder 41.

The DCO 29 consists of the adder 41 and a register 45 connected asindicated so as to form an accumulator wherein the sum of the frequencysetter 43 and the error adder 39 is added to itself at each clock pulseuntil the register 45 is filled. It is evident that such a connectioncauses the output of the register 45 to increase in a linear arithmeticprogression with each clock pulse, the steps in such progression beingequal to the sum of the input signals to the adder 41. Therefore, thenumber of clock pulses required to cause register 45 to be filled, i.e.,the period of the DCO 29, is dependent on the sum of the signals out ofthe error adder 39 and the frequency setter 43. The register 45 is alsoconnected, as shown, through AND gate 46, to pass pulses to a counter47. The latter element, therefore, counts each register filled signalfrom the register 45. It is noted that the register 45 recyclesautomatically because signals from the error adder 39 and the frequencysetter 43 maintain an input to the register 45. On the other hand, thecounter 47 repetitively counts up from zero to a filled condition andthen resets itself to zero as long as clock pulses are applied to theadder 41 and the register 45. The signal out of the counter 47 is fed toa decoder 51, which preferably consists of conventional diode decodingnetworks (not shown) to combine the output of the various stages of thecounter 47 so that that component operates as a binary divider, countingrepetitively, the last stage being at the DCO frequency and the next tolast stage being at twice the DCO frequency. Thus, if the normal andcomplementary outputs of the last two stages are passed through aconventional exclusive OR gating arrangement, a symmetrical square waveshifted in phase by from the normal output of the last stage is derived.Such a phase shifted wave is derived and applied to the exclusive ORgate 25 as shown.

The binary signal (unshifted) from the normal output of the last stageof the decoder 51 is fed, as shown, to a digital/analog converter 53wherein such signal is converted to a sine wave having a period equal tothe period of the last stage of the decoder 51. The resulting sine waveis then fed through a detector 55 and thence to a utilization device 57.The latter two elements may, for example, be a conventional detector andindicator.

As indicated, the binary signal (unshifted) from the normal output ofthe last stage of the decoder 51 is also fed to one input of exclusiveOR gate 25a. As noted hereinbefore, the other input to exclusive OR gate25a preferably is the same as exclusive OR gate 25. The output ofexclusive OR gate 25a is fed through an inverter 59 and a low passfilter 61 to lock indicator 63. The low pass filter 59 preferably is asimple R-C circuit while the lock indicator 63 may be an indicator lamp.When a phase lock exists, the inputs to the exclusive OR gate 250 areidentical and its output is low. This low output is inverted to a highsignal by the inverter 59 and, after passing through the low pass filter61, energizes the lock indicator 63. When there is no phase lock, theoutput of the inverter 59 decreases and, as a result, the lock indicator63 is not energized. The low pass filter 61 prevents transients, as mayoccur when the described circuit is operating to phase lock the DCO 29with the signal out of the limiting amplifier 19 or when noiseperturbates the latter signal, from energizing the lock indicator 63.

Having described a preferred embodiment of this invention, it will beclear to those of skill in the art that alternative embodiments willequally well fulfill the concepts hereof. For example, the particularDCO shown may be replaced by any known DCO. Further, it will be evidentthat conventional synchronizing circuitry may be added to eliminate thepossibility of misalignment between clock pulses and signals beingprocessed. Still further, the output of the disclosed speed gate may beused for purposes other than that shown, as, for example, the inputsignal to a Doppler processor. It is felt, therefore, that thisinvention should not be restricted to its disclosed embodiment, butrather should be limited only by the spirit and scope of the appendedclaims.

What is claimed is:

1. For use in the receiver of a Doppler radar, frequency trackingcircuitry for locking the output signal of a digitally controlledoscillator with an echo signal from a selected target, such echo signalbeing amplitude limited, such circuitry comprising:

a. an'exclusive OR gate, responsive to the output signal and to the echosignal, for producing a square wave signal, the degree of asymmetrythereof being indicative of the difference in a frequency between thetwo applied signals;

b. means for producing a digital correction signal proportional to thedegree of asymmetry of the square wave signal; and,

0. means, responsive to the digital correction signal, for changing thefrequency of the output signal of the digitally controlled oscillator toreduce the degree of asymmetry of the square wave signal to a minimum.

2. Frequency tracking circuitry as in claim 1 wherein the first-namedmeans includes:

a. a clock pulse generator for producing clock pulses at the Nyquistrate for the echo signal having the highest frequency;

b. first and second gating means, enabled during mutually exclusiveperiods of time during each reception time of an echo signal by thesquare wave signal for passing clock pulses;

c. a binary up-down counter, responsive to the clock pulses passed bythe first and the second gating means, for counting the differencebetween the number of clock pulses passed by the first gating means andthe number of clock pulses passed by the second gating means to derivean average difference count during a plurality of reception times; and,

. a binary adder, responsive to the average difference count in thebinary up-down counter and to the clock pulses passed by the first andthe second gating means, for producing the digital cor rection signal.

3. Frequency tracking circuitry as in claim 2 having, additionally:

a. means, responsive to the output signal of the digitally controlledoscillator, for producing a digital indicating signal corresponding tothe digital correction signal but displaced in phase therefrom by and,

b. means, responsive to the digital indicating signal and to the echosignal, for indicating when the two are in phase.

4. Frequency tracking circuitry as in claim 3 having, additionally,means, responsive to the digital indicating signal, for converting suchsignal to a sine wave signal oflike periodicity.

1. For use in the receiver of a Doppler radar, frequency trackingcircuitry for locking the output signal of a digitally controlledoscillator with an echo signal from a selected target, such echo signalbeing amplitude limited, such circuitry comprising: a. an exclusive ORgate, responsive to the output signal and to the echo signal, forproducing a square wAve signal, the degree of asymmetry thereof beingindicative of the difference in a frequency between the two appliedsignals; b. means for producing a digital correction signal proportionalto the degree of asymmetry of the square wave signal; and, c. means,responsive to the digital correction signal, for changing the frequencyof the output signal of the digitally controlled oscillator to reducethe degree of asymmetry of the square wave signal to a minimum.
 1. Foruse in the receiver of a Doppler radar, frequency tracking circuitry forlocking the output signal of a digitally controlled oscillator with anecho signal from a selected target, such echo signal being amplitudelimited, such circuitry comprising: a. an exclusive OR gate, responsiveto the output signal and to the echo signal, for producing a square wAvesignal, the degree of asymmetry thereof being indicative of thedifference in a frequency between the two applied signals; b. means forproducing a digital correction signal proportional to the degree ofasymmetry of the square wave signal; and, c. means, responsive to thedigital correction signal, for changing the frequency of the outputsignal of the digitally controlled oscillator to reduce the degree ofasymmetry of the square wave signal to a minimum.
 2. Frequency trackingcircuitry as in claim 1 wherein the first-named means includes: a. aclock pulse generator for producing clock pulses at the Nyquist rate forthe echo signal having the highest frequency; b. first and second gatingmeans, enabled during mutually exclusive periods of time during eachreception time of an echo signal by the square wave signal for passingclock pulses; c. a binary up-down counter, responsive to the clockpulses passed by the first and the second gating means, for counting thedifference between the number of clock pulses passed by the first gatingmeans and the number of clock pulses passed by the second gating meansto derive an average difference count during a plurality of receptiontimes; and, d. a binary adder, responsive to the average differencecount in the binary up-down counter and to the clock pulses passed bythe first and the second gating means, for producing the digitalcorrection signal.
 3. Frequency tracking circuitry as in claim 2 having,additionally: a. means, responsive to the output signal of the digitallycontrolled oscillator, for producing a digital indicating signalcorresponding to the digital correction signal but displaced in phasetherefrom by 90*; and, b. means, responsive to the digital indicatingsignal and to the echo signal, for indicating when the two are in phase.